US 12,437,138 B2
Layout method of semiconductor chip, semiconductor chip manufacturing method and computing device using same
Akio Misaka, Hwaseong-si (KR); Noyoung Chung, Hwaseong-si (KR); Taekyum Kim, Suwon-si (KR); Sanghwa Lee, Seoul (KR); and Woonhyuk Choi, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 7, 2022, as Appl. No. 17/961,710.
Claims priority of application No. 10-2021-0185672 (KR), filed on Dec. 23, 2021.
Prior Publication US 2023/0205963 A1, Jun. 29, 2023
Int. Cl. G06F 30/392 (2020.01); G06F 30/398 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A layout method of a semiconductor chip, comprising:
designing a layout using a restriction rule such that a layout pattern having a length smaller than a first length in a first direction has to have a length smaller than a second length in a second direction, the second direction intersecting the first direction;
generating a plurality of unit regions by partitioning the layout in the first direction;
generating a plurality of target regions by adding a reference region to a partitioned edge of each of the plurality of unit regions;
retargeting the plurality of target regions in parallel; and
generating a correction layout by merging the plurality of retargeted target regions.