US 12,437,121 B2
Efficient processing of masked memory accesses
Andrew Waterman, Berkeley, CA (US); and Krste Asanovic, Oakland, CA (US)
Assigned to SiFive, Inc., Santa Clara, CA (US)
Appl. No. 18/023,948
Filed by SiFive, Inc., San Mateo, CA (US)
PCT Filed Sep. 1, 2021, PCT No. PCT/US2021/048599
§ 371(c)(1), (2) Date Feb. 28, 2023,
PCT Pub. No. WO2022/051325, PCT Pub. Date Mar. 10, 2022.
Claims priority of provisional application 63/073,912, filed on Sep. 2, 2020.
Prior Publication US 2024/0012948 A1, Jan. 11, 2024
Int. Cl. G06F 21/78 (2013.01); G06F 9/30 (2018.01)
CPC G06F 21/78 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 2212/1041 (2013.01); G06F 2212/1052 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit for executing instructions comprising:
a processor core including a pipeline configured to execute masked vector memory instructions; and
a memory protection circuit configured to check for memory protection violations, the memory protection circuit configured to:
monitor the masked vector memory instructions;
perform a memory protection violation check, during scalar processing, based on a memory footprint of a masked vector memory instruction while ignoring mask information associated with a vector identified by the masked vector memory instruction;
after performing the memory protection violation check, perform memory protection violation checks, during vector processing, on vector elements of the vector in the event of a memory protection violation or speculative access is denied based on the memory footprint; and
based on the memory protection violation checks, perform one of:
raise a fault exception when a mask bit is enabled and a memory violation is detected for a vector element; or
continue with execution of the masked vector memory instruction when no memory protection violations are detected for the vector elements.