US 12,437,095 B2
Register interface for computer processor
Stanley Chen, Portland, OR (US); Vivek Garg, Folsom, CA (US); Ankush Varma, Portland, OR (US); Eric J. Dehaemer, Shrewsbury, MA (US); and Johan van de Groenendaal, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 20, 2021, as Appl. No. 17/645,070.
Prior Publication US 2023/0195918 A1, Jun. 22, 2023
Int. Cl. G06F 21/62 (2013.01); G06F 9/30 (2018.01)
CPC G06F 21/6218 (2013.01) [G06F 9/30101 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A processor comprising:
at least one processing engine to execute instructions; and
a register interface circuit coupled to the at least one processing engine, the register interface circuit to:
receive a request to access a register associated with a feature of the processor;
determine whether the requested access is authorized based at least in part on an entry of an access structure, the access structure to store a plurality of entries associated with a plurality of features of the processor, wherein the register interface circuit is to:
identify a source entity type as an in-band or out-of-band software entity for the request, identify an access type of the request, determine whether the access structure indicates that the access type is authorized for the source entity type, and determine that the requested access is authorized in response to a determination that the access type is authorized for the source entity type; and
in response to a determination that the requested access is authorized by the access structure, perform the requested access of the register associated with the feature.