US 12,437,056 B2
Transaction process between an application and a device
Michel Jaouen, Yvre l'Eveque (FR)
Assigned to STMICROELECTRONICS (GRAND OUEST) SAS, Le Mans (FR)
Filed by STMicroelectronics (Grand Ouest) SAS, Le Mans (FR)
Filed on Oct. 24, 2022, as Appl. No. 18/048,940.
Claims priority of application No. 2111294 (FR), filed on Oct. 25, 2021.
Prior Publication US 2023/0127971 A1, Apr. 27, 2023
Int. Cl. G06F 21/54 (2013.01); G06F 9/30 (2018.01); G06F 21/55 (2013.01)
CPC G06F 21/54 (2013.01) [G06F 9/30101 (2013.01); G06F 21/554 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A circuit comprising:
a cryptographic circuit comprising configuration registers; and
a processor configured to execute a hardware abstraction layer and an application configured to communicate with the cryptographic circuit via the hardware abstraction layer, wherein:
the hardware abstraction layer is configured to configure the cryptographic circuit for a transaction by writing, in the configuration registers, a cryptography key provided by the application,
the cryptographic circuit is configured to generate a hash value in a register of the cryptographic circuit after the configuration of the cryptographic circuit based on the cryptography key written in the configuration registers, and
the hardware abstraction layer is further configured to:
read the hash value written in the register of the cryptographic circuit, and calculate a first transformed hash value from the read hash value by calculating a one's complement of the read hash value, and
the cryptographic circuit is further configured to
calculate a second transformed hash value from the hash value written in the register of the cryptographic circuit by calculating the one's complement of the hash value written in the register of the cryptographic circuit,
compare the first transformed hash value calculated by the hardware abstraction layer with the second transformed hash value calculated by the cryptographic circuit, and
execute the transaction only when the first transformed hash value calculated by the hardware abstraction layer is equal to the second transformed hash value calculated by the cryptographic circuit.