US 12,437,026 B1
System having multiple buses and method for controlling processing core in the system
Je Ik Choi, Pyeongtaek-si (KR)
Assigned to DEEPX CO., LTD., Seongnam-si (KR)
Filed by DEEPX CO., LTD., Seongnam-si (KR)
Filed on Apr. 11, 2025, as Appl. No. 19/176,288.
Claims priority of application No. 10-2024-0183303 (KR), filed on Dec. 11, 2024.
Int. Cl. G06F 17/16 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01)
CPC G06F 17/16 (2013.01) [G06F 13/16 (2013.01); G06F 13/42 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
at least one processing core configured to perform computation operations on input tensors to generate output tensors, the input tensors and the output tensors associated with at least one neural network model;
at least one memory circuit configured to store the input tensors and the output tensors;
a plurality of bus circuits operably coupled to the at least one processing core and the at least one memory circuit, the plurality of bus circuits configured to:
send the input tensors from the at least one memory circuit to the at least one processing core responsive to receiving requests for read operations, and
send the output tensors from the at least one processing core to the at least one memory circuit responsive to receiving requests for write operations; and
a controller operably coupled to the plurality of bus circuits, the controller configured to:
determine whether data starvation has occurred or is predicted to occur in the at least one processing core,
determine priority of the read operations of each of the input tensors or the write operations of each of the output tensors responsive to determining whether the data starvation has occurred or is predicted to occur in the processing core, and
control the plurality of bus circuits to send each of the input tensors or each of the output tensors according to the determined priority.