US 12,436,907 B2
Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules
Frederick A. Ware, Los Altos Hills, CA (US); Ely Tsern, Los Altos, CA (US); John Eric Linstadt, Palo Alto, CA (US); Thomas J. Giovannini, San Jose, CA (US); and Kenneth L. Wright, Sunnyvale, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc, San Jose, CA (US)
Filed on Oct. 6, 2023, as Appl. No. 18/482,268.
Application 18/482,268 is a continuation of application No. 17/748,762, filed on May 19, 2022, granted, now 11,815,940.
Application 17/748,762 is a continuation of application No. 17/100,560, filed on Nov. 20, 2020, granted, now 11,341,070, issued on May 24, 2022.
Application 17/100,560 is a continuation of application No. 16/290,375, filed on Mar. 1, 2019, granted, now 10,846,252, issued on Nov. 24, 2020.
Application 16/290,375 is a continuation of application No. 15/533,630, granted, now 10,223,309, issued on Mar. 5, 2019, previously published as PCT/US2015/057822, filed on Oct. 28, 2015.
Claims priority of provisional application 62/234,409, filed on Sep. 29, 2015.
Claims priority of provisional application 62/233,884, filed on Sep. 28, 2015.
Claims priority of provisional application 62/220,101, filed on Sep. 17, 2015.
Claims priority of provisional application 62/094,914, filed on Dec. 19, 2014.
Prior Publication US 2024/0104036 A1, Mar. 28, 2024
Int. Cl. G06F 13/28 (2006.01); G06F 13/16 (2006.01); G11C 5/02 (2006.01); G11C 5/04 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 29/02 (2006.01)
CPC G06F 13/287 (2013.01) [G06F 13/16 (2013.01); G11C 5/04 (2013.01); G11C 7/10 (2013.01); G11C 7/1045 (2013.01); G06F 2213/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory stack comprising:
a first memory die comprising:
a first set of memory cells;
a first data interface;
a second data interface; and
first steering circuitry coupled to the first set of memory cells, the first data interface, and the second data interface; and
a second memory die comprising:
a second set of memory cells;
a third data interface;
a fourth data interface coupled to the second data interface using a first set of through-silicon-via (TSV) connections; and
second steering circuitry coupled to the second set of memory cells, the third data interface, and the fourth data interface, wherein the first memory die and the second memory die are homogeneous.