US 12,436,906 B1
Multi-threaded data movement request handling
Mohammad El-Shabani, Redwood City, CA (US); Ron Diamant, Santa Clara, CA (US); Henry Wang, San Bruno, CA (US); and Zhao Ma, San Jose, CA (US)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Jun. 3, 2022, as Appl. No. 17/805,428.
Int. Cl. G06F 13/28 (2006.01); G06F 9/30 (2018.01); G06F 9/52 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/28 (2013.01) [G06F 9/3009 (2013.01); G06F 9/522 (2013.01); G06F 13/1673 (2013.01); G06F 13/1689 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for handling data movement requests at a direct memory access (DMA) engine of an integrated circuit device, the computer-implemented method comprising:
allocating a first data movement request to a first data movement request handling thread by placing the first data movement request in a first data movement request queue, wherein the first data movement request is requesting a first data movement task that includes a first data movement phase having a first set of one or more data movement operations, and a first sync phase having a first sync operation;
allocating a second data movement request to a second data movement request handling thread by placing the second data movement request in a second data movement request queue, wherein the second data movement request is requesting a second data movement task that includes a second data movement phase having a second set of one or more data movement operations, and a second sync phase having a second sync operation;
performing, by the DMA engine, the first set of one or more data movement operations;
during a wait period for the first sync phase, performing, by the DMA engine, the second set of one or more data movement operations; and
during a wait period for the second sync phase and following the wait period for the first sync phase, initiating, by the DMA engine, the first sync phase and performing the first sync operation.