US 12,436,904 B2
Storing feature vectors in one or more memory processing units
Eliad Hillel, Herzliya (IL); Shany Braudo, Tel Aviv (IL); Gal Dayan, Hod Hasharon (IL); and Shay Koren, Tel Aviv (IL)
Assigned to NeuroBlade Ltd., Tel Aviv (IL)
Filed by NEUROBLADE LTD., Tel Aviv (IL)
Filed on Apr. 7, 2023, as Appl. No. 18/297,229.
Application 18/297,229 is a continuation of application No. PCT/US2021/055472, filed on Oct. 18, 2021.
Claims priority of provisional application 63/230,212, filed on Aug. 6, 2021.
Claims priority of provisional application 63/093,968, filed on Oct. 20, 2020.
Claims priority of provisional application 63/092,658, filed on Oct. 16, 2020.
Claims priority of provisional application 63/198,426, filed on Oct. 16, 2020.
Claims priority of provisional application 63/198,429, filed on Oct. 16, 2020.
Claims priority of provisional application 63/092,689, filed on Oct. 16, 2020.
Claims priority of provisional application 63/092,671, filed on Oct. 16, 2020.
Claims priority of provisional application 63/092,682, filed on Oct. 16, 2020.
Claims priority of provisional application 63/092,647, filed on Oct. 16, 2020.
Prior Publication US 2023/0259584 A1, Aug. 17, 2023
Int. Cl. G06F 17/16 (2006.01); G06F 9/50 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 16/75 (2019.01)
CPC G06F 13/1694 (2013.01) [G06F 9/5016 (2013.01); G06F 11/1044 (2013.01); G06F 13/1668 (2013.01); G06F 13/404 (2013.01); G06F 17/16 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A computational memory system, comprising:
at least one computational memory chip including one or more processor subunits and one or more memory banks formed on a common substrate;
wherein the at least one computational memory chip is configured to store one or more portions of an embedding table in the one or more memory banks, the embedding table including one or more feature vectors;
wherein the one or more processor subunits are configured to receive a sparse vector indicator from a host external to the at least one computational memory chip and, based on the received sparse vector indicator and the one or more portions of the embedding table, generate one or more vector sums; and
wherein the one or more processor subunits and the one or more memory banks of the at least one computational memory chip are arranged into a plurality of computational memory groups, wherein each computational memory group includes at least one processor subunit and one or more of the memory banks dedicated to the at least one processor subunit.