US 12,436,898 B2
Cache injection and prefetch mechanisms for improving multi-die processing system performance
Shaju Abraham, Bangalore (IN); Akash A, Bengaluru (IN); Naveen M, Bangalore (IN); and Shreeroop Ajaykumar, Kannur (IN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 12, 2023, as Appl. No. 18/537,154.
Prior Publication US 2025/0190367 A1, Jun. 12, 2025
Int. Cl. G06F 12/00 (2006.01); G06F 12/0811 (2016.01); G06F 12/128 (2016.01); G06F 12/0862 (2016.01)
CPC G06F 12/128 (2013.01) [G06F 12/0811 (2013.01); G06F 12/0862 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a history buffer configured to store, for a fixed time, cache line addresses; and
a processor core connected to the history buffer, the processor core configured to flush, after the fixed time, the cache line addresses from the history buffer and add new cache line addresses into the history buffer.