US 12,436,897 B2
Cache management using eviction priority based on memory reuse
Noam Dor Korem, Tal-El (IL); Brian Scott Pharris, Cary, NC (US); and Jacob Subag, Haifa (IL)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Mar. 7, 2023, as Appl. No. 18/180,008.
Prior Publication US 2024/0303203 A1, Sep. 12, 2024
Int. Cl. G06F 12/12 (2016.01); G06F 12/126 (2016.01); G06N 3/0464 (2023.01)
CPC G06F 12/126 (2013.01) [G06N 3/0464 (2023.01)] 20 Claims
OG exemplary drawing
 
1. A method of managing a cache located on a processor, the method comprising:
identifying a plurality of memory addresses associated with a workload of an application executing using the processor;
determining a characteristic of the workload that corresponds to an amount of traffic between the cache and off-chip memory generated at one or more memory addresses of the plurality of memory addresses;
determining an amount of reuse of the plurality of memory addresses using the characteristic;
determining a cache management policy for the workload based on the amount of reuse; and
applying the cache management policy to the cache.