US 12,436,896 B1
AI accelerator integrated circuit chip with integrated cell-based fabric adapter
Gary S. Goldman, Los Altos, CA (US); Ramalingam K. Anand, Los Altos Hills, CA (US); Kalyana S. Venkataraman, San Jose, CA (US); Berend Ozceri, Los Gatos, CA (US); Pradeep R. Joginipally, San Jose, CA (US); Chung Y. Lau, Milpitas, CA (US); Jigar K. Savla, San Jose, CA (US); Ashwin Radhakrishnan, Fremont, CA (US); Michael Davie, St Augustine, FL (US); and Shijun Li, Southborough, MA (US)
Assigned to Recogni Inc., San Jose, CA (US)
Filed by Recogni Inc., San Jose, CA (US)
Filed on Dec. 20, 2024, as Appl. No. 18/989,492.
Claims priority of provisional application 63/694,397, filed on Sep. 13, 2024.
Int. Cl. G06F 13/36 (2006.01); G06F 12/1081 (2016.01); G06F 13/40 (2006.01)
CPC G06F 12/1081 (2013.01) [G06F 13/4068 (2013.01); G06F 13/409 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package, the integrated circuit comprising:
a communication interface;
a fabric adapter communicatively coupled to the communication interface;
a plurality of inference engine clusters, each inference engine cluster including a respective memory element; and
a data interconnect communicatively coupling each respective memory element of the plurality of inference engine clusters to the fabric adapter,
wherein the fabric adapter is configured to facilitate remote direct memory access (RDMA) read and write services over a cell-based switch fabric to and from the respective memory elements of the plurality of inference engine clusters via the data interconnect,
wherein the cell-based switch fabric comprises a plurality of cell-fabric switch chips that are disposed external to the integrated circuit, and
wherein the fabric adapter comprises a virtual output queue (VOQ) subsystem.