US 12,436,891 B1
Allocation of store buffer entries
Ilaria Bosco, Nice (FR); Yohan Fernand Fargeix, Nice (FR); Geoffray Matthieu Lacourba, Nice (FR); Paolo Monti, Quattordio (IT); Luca Nassi, Antibes (FR); and Albin Pierrick Tonnerre, Nice (FR)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Jun. 25, 2024, as Appl. No. 18/753,357.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0871 (2016.01); G06F 12/0875 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/0871 (2013.01) [G06F 12/0875 (2013.01); G06F 13/1673 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus comprising:
allocation circuitry configured to allocate store data in a store buffer, the store data comprising N portions, where N>1;
the store buffer comprising:
a data buffer configured to hold data entries, each data entry configured to hold one of the N portions of the store data;
an address buffer configured to hold address entries, wherein a given address entry is indicative of a memory address at which the store data is to be stored and is associated with N indications identifying one or more of the data entries that contain the store data;
wherein the allocation circuitry is responsive to a determination that M portions of the N portions of the store data each comprise duplicate data to set M indications of the N indications to identify a given data entry holding the duplicate data.