US 12,436,889 B1
Cache circuit that selectively stores data blocks to dynamically optimize for read and write transactions
Saurabh Kumar Shrimal, Noida (IN); Sandeep Dager, Ghaziabad (IN); Ravindra Kumar, Bengaluru (IN); and Sahil Pandey, New Delhi (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 2, 2024, as Appl. No. 18/793,111.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) 24 Claims
OG exemplary drawing
 
1. A cache circuit configured to couple to a memory circuit, the cache circuit comprising:
a plurality of read address registers configured to store memory addresses of data blocks requested from a memory circuit in most recent memory read transactions;
a plurality of write address registers configured to store memory addresses of data blocks written to the memory circuit in most recent memory write transactions;
a plurality of data registers configured to selectively store, based on a mode count, the data blocks requested from the memory circuit in the most recent memory read transactions and the data blocks written to the memory circuit in the most recent memory write transactions; and
a control circuit configured to:
receive a first memory read transaction requesting a first data block at a first memory address;
generate a hit signal in an active state in response to determining that the first data block is stored in the plurality of data registers;
return the first data block from the plurality of data registers in response to the hit signal; and
adjust the mode count based on the first memory address.