US 12,436,885 B2
Systems and methods for scalable and coherent memory devices
Krishna T. Malladi, San Jose, CA (US); Andrew Chang, Los Altos, CA (US); and Ehsan Najafabadi, San Jose, CA (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 24, 2023, as Appl. No. 18/357,798.
Application 18/357,798 is a continuation of application No. 17/246,448, filed on Apr. 30, 2021.
Claims priority of provisional application 63/068,054, filed on Aug. 20, 2020.
Claims priority of provisional application 63/057,746, filed on Jul. 28, 2020.
Claims priority of provisional application 63/031,509, filed on May 28, 2020.
Claims priority of provisional application 63/031,508, filed on May 28, 2020.
Prior Publication US 2023/0367711 A1, Nov. 16, 2023
Int. Cl. G06F 12/06 (2006.01); G06F 9/30 (2018.01); G06F 9/445 (2018.01); G06F 12/0891 (2016.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01)
CPC G06F 12/0646 (2013.01) [G06F 9/30047 (2013.01); G06F 9/44505 (2013.01); G06F 12/0891 (2013.01); G06F 13/1668 (2013.01); G06F 13/4234 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a first controller operable with a memory protocol and coupled to a network;
a second controller coupled to the first controller and coupled to a first memory, the second controller performing an operation associated with a cache of the device, the second controller being configured, by the device, to operate as a first type of cache, based on receiving configuration information; and
a module that determines memory-access-pattern information and a capability associated with the device and transmits the memory-access-pattern information and the capability to another device.