US 12,436,880 B2
Selective single-level memory cell operation
Donghua Zhou, Suzhou (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 19, 2023, as Appl. No. 18/545,561.
Application 18/545,561 is a continuation of application No. 17/824,725, filed on May 25, 2022, granted, now 11,853,201.
Prior Publication US 2024/0134788 A1, Apr. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/02 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 2212/7206 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
configuring a first subset of non-volatile memory blocks of a non-volatile memory to collectively operate as a pseudo single-level cache responsive to detection of a backup power supply failure event;
writing data associated with a memory operation to the first subset of non-volatile memory blocks configured as the pseudo single-level cache; and
migrate the data from the first subset to a second subset of non-volatile memory blocks of the non-volatile memory.