US 12,436,876 B2
Memory management system
Sean Lee, Kirkland, WA (US); Vinod Grover, Mercer Island, WA (US); and James Clarkson, Tewkesbury (GB)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Feb. 19, 2019, as Appl. No. 16/279,884.
Prior Publication US 2020/0264970 A1, Aug. 20, 2020
Int. Cl. G06F 12/02 (2006.01); G06F 3/06 (2006.01)
CPC G06F 12/023 (2013.01) [G06F 3/0608 (2013.01); G06F 3/0631 (2013.01); G06F 3/067 (2013.01); G06F 2212/1044 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A method, comprising:
using one or more circuits of a processor to cause the processor to partition and store data in a plurality of storage locations based, at least in part, upon one or more dependencies between two or more processor instructions.