US 12,436,858 B2
Scan synchronous-write-through testing architectures for a memory device
Ming-Hung Chang, Tainan (TW); Atul Katoch, Kanata (CA); Chia-En Huang, Hsinchu County (TW); Ching-Wei Wu, Nantou County (TW); Donald G. Mikan, Jr., Austin, TX (US); Hao-I Yang, Taipei (TW); Kao-Cheng Lin, Taipei (TW); Ming-Chien Tsai, Kaohsiung (TW); Saman M. I. Adham, Kanata (CA); Tsung-Yung Chang, Hsinchu (TW); and Uppu Sharath Chandra, Austin, TX (US)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 28, 2023, as Appl. No. 18/342,819.
Application 18/342,819 is a continuation of application No. 17/651,595, filed on Feb. 18, 2022, granted, now 11,734,142.
Application 17/651,595 is a continuation of application No. 16/888,013, filed on May 29, 2020, granted, now 11,256,588, issued on Feb. 22, 2022.
Application 16/888,013 is a continuation of application No. 15/700,877, filed on Sep. 11, 2017, granted, now 10,705,934, issued on Jul. 7, 2020.
Claims priority of provisional application 62/527,331, filed on Jun. 30, 2017.
Prior Publication US 2023/0342272 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/263 (2006.01); G06F 1/10 (2006.01); G06F 11/22 (2006.01); G06F 11/267 (2006.01); G11C 29/12 (2006.01); G11C 29/32 (2006.01); G11C 29/48 (2006.01)
CPC G06F 11/263 (2013.01) [G06F 1/10 (2013.01); G06F 11/2273 (2013.01); G06F 11/267 (2013.01); G11C 29/1201 (2013.01); G11C 29/32 (2013.01); G11C 29/48 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a first circuit coupled to a memory device and configured to provide an input sequence of test data to the memory device based on a selection between a serial sequence of input data and a parallel sequence of input data, wherein the first circuit comprises a first multiplexing circuit and a latching circuit;
a second circuit configured to receive the input sequence of test data from the first circuit and to provide a serial sequence of output data; and
a third circuit coupled to the memory device and the second circuit and configured to compare an output sequence of test data provided by the memory device to the serial sequence of output data to test an operation of the memory device, wherein the third circuit comprises a second multiplexing circuit and a functional logic circuit.