US 12,436,838 B2
Memory controller and memory system including the same
Jae Yong Son, Gyeonggi-do (KR); Dae Sung Kim, Gyeonggi-do (KR); and Min Su Choi, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Aug. 10, 2023, as Appl. No. 18/447,326.
Claims priority of application No. 10-2023-0021639 (KR), filed on Feb. 17, 2023.
Prior Publication US 2024/0281321 A1, Aug. 22, 2024
Int. Cl. G06F 11/10 (2006.01)
CPC G06F 11/10 (2013.01) 17 Claims
OG exemplary drawing
 
9. A method of operating a memory controller, comprising:
sequentially performing first to k-th read retry operations among first to n-th read retry operations;
storing first to k-th read retry voltages used for the respective first to k-th read retry operations and first to k-th syndrome weights corresponding to the respective first to k-th read retry voltages;
determining, when the first to k-th read retry operations fail, a minimum syndrome weight based on a relationship between changes in the first to k-th syndrome weights relative to the first to k-th read retry voltages;
determining an optimally estimated read voltage corresponding to the minimum syndrome weight;
reading data stored in a memory device using the optimally estimated read voltage, the reading the data stored in the memory device comprising performing hard decision decoding of correcting errors in the data that is read using the optimally estimated read voltage; and
performing, when the hard decision decoding fails, soft decision decoding on data that is read using soft read voltages having respective offset values based on the optimally estimated read voltage.