US 12,436,818 B2
Disabling a processor facility on a new processor generation without breaking binary compatibility
Brian Frank Veale, Cedar Park, TX (US); Arnold Flores, Round Rock, TX (US); Andre Laurent Albot, Austin, TX (US); and Juan M. Casas, Jr., Round Rock, TX (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Aug. 24, 2022, as Appl. No. 17/821,832.
Prior Publication US 2024/0069980 A1, Feb. 29, 2024
Int. Cl. G06F 9/50 (2006.01)
CPC G06F 9/5077 (2013.01) [G06F 9/5088 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
performing a first migration of a first running logical partition (LPAR) from a first-generation computer to a second-generation computer, where an availability of a facility differs between the first-generation computer and the second-generation computer, and wherein an operating system of the first running LPAR is actively executing the facility during the first migration;
upon completion of the first migration, the operating system of the first running LPAR detecting whether a required facility in use on the first-generation computer is available on the second-generation computer; and
based on the required facility being available on the second-generation computer, the operating system continuing execution of the first running LPAR;
based on the required facility not being available on the second-generation computer, the operating system continuing execution of the required facility in emulation mode until work requiring the required facility completes, after which the operating system intercepts attempts to execute the required facility, signals an illegal operation to a calling process; and
terminating the calling process in response to the calling process not executing a signal handler.