US 12,436,808 B2
CPU tight-coupled accelerator
Zhi-Gang Liu, Westford, MA (US); Jun Woo Jang, Santa Clara, CA (US); Sehwan Lee, Seongnam-si (KR); and Dongkyun Kim, Fremont, CA (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 21, 2023, as Appl. No. 18/225,041.
Claims priority of provisional application 63/471,443, filed on Jun. 6, 2023.
Prior Publication US 2024/0411599 A1, Dec. 12, 2024
Int. Cl. G06F 9/48 (2006.01); G06F 9/50 (2006.01)
CPC G06F 9/5027 (2013.01) [G06F 9/4881 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a central processing unit (CPU) core;
an accelerator; and
an acceleration instruction queue connected to the CPU core and the accelerator,
wherein the CPU core is configured to:
fetch and decode one or more instructions from among an instruction sequence in a programmed order, the one or more instructions comprising an acceleration workload for the accelerator and a CPU workload for the CPU core;
determine a first instruction from among the one or more instructions containing the acceleration workload encoded therein based on an instruction type of the first instruction indicating the acceleration workload;
queue the first instruction containing the acceleration workload encoded therein in the acceleration instruction queue;
determine a second instruction from among the one or more instructions containing the CPU workload therein based on an instruction type of the second instruction indicating the CPU workload; and
dispatch the second instruction to a CPU data path for the CPU core, and
wherein the instruction type indicating the acceleration workload comprises one or more tensor operations, and the instruction type indicating the CPU workload comprises at least one of a scalar workload, a vector workload, or a memory workload.