| CPC G06F 9/5016 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30098 (2013.01); G06F 9/5044 (2013.01)] | 4 Claims |
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1. A computer system, comprising:
a processor, comprising an embedded memory; and
a processing circuit, arranged to perform a write operation for writing a first write data into the embedded memory included in the processor;
wherein the processor is arranged to load and execute a program code, to perform a read operation for reading the first write data from the embedded memory included in the processor;
wherein the embedded memory has a storage space addressed by a memory address; the processing circuit writes the first write data into the storage space; and before notifying the processing circuit of writing the first write data into the embedded memory, the processor executes the program code to write an invalid code into the storage space;
wherein after notifying the processing circuit of writing the first write data into the embedded memory, the processor executes the program code to read a read data from the memory address, and compares the read data with the invalid code to generate a comparison result; in response to the comparison result indicating that the read data is different from the invalid code, the processor executes the program code to write the invalid code into the memory address again, and writes the read data back to a register comprised in the processing circuit, in order to notify the processing circuit via the register that a next data can be written into the embedded memory; and in response to the comparison result indicating that the read data is not different from the invalid code, the processor executes the program code to wait for the processing circuit to write the first write data into the embedded memory, and executes the program code to process other tasks.
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