| CPC G06F 9/3836 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30043 (2013.01)] | 20 Claims |
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1. A method comprising:
receiving, in a dispatch unit of a processor, a sequence of instructions having a program order, wherein at least some of the instructions are vector load instructions to load data from a memory system into a vector register file of the processor;
dispatching the instructions from the dispatch unit to a plurality of issue queues in the processor, wherein dispatching the instructions includes dispatching each vector load instruction to a load/store issue queue of a load/store unit of the processor and to a vector issue queue in a vector domain of the processor;
determining, by the load/store unit, whether each vector load instruction in the load/store issue queue is ready for issue, the determination including a constraint that the vector load instruction is within or younger than a clearance window defined within the load/store issue queue, wherein the clearance window is defined to allow at least some of the vector load instructions to be executed by the load/store unit out of the program order with respect to each other;
executing, by the load/store unit, instructions from the load/store issue queue in an order different from the program order, wherein execution of the vector load instruction by the load/store unit occurs while the vector load instruction is ready for execution and wherein executing the vector load instruction by the load/store unit includes allocating a space in a vector transfer buffer and loading data from memory into the allocated space in the vector transfer buffer; and
executing, in the vector domain of the processor, instructions from the vector issue queue in the program order, wherein execution of the vector load instruction in the vector domain includes transferring data from the allocated space in the vector transfer buffer to a destination register in the vector register file.
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