US 12,436,767 B2
System and method for scheduling operations in a graphics pipeline
Matthäus G. Chajdas, Munich (DE); Michael J. Mantor, Orlando, FL (US); Rex Eldon McCrary, Orlando, FL (US); Christopher J. Brennan, Boxborough, MA (US); Robert Martin, Boxborough, MA (US); and Brian Kenneth Bennett, Boxborough, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 14, 2022, as Appl. No. 18/066,115.
Prior Publication US 2024/0202003 A1, Jun. 20, 2024
Int. Cl. G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06T 1/20 (2006.01)
CPC G06F 9/3836 (2013.01) [G06F 9/3826 (2013.01); G06F 9/3867 (2013.01); G06F 9/4881 (2013.01); G06T 1/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a pipeline comprising one or more fixed-function units comprising circuitry; and
an output buffer corresponding to the pipeline and configured to store data received from an end of the pipeline; and
a scheduler comprising circuitry configured to:
receive a first operation to be executed by a first fixed-function unit of the pipeline;
cause the first operation to be executed, and generate an output, by the first fixed-function unit;
retrieve the output from the output buffer, responsive to a first mode of operation; and
retrieve the output from the first fixed-function unit instead of the output buffer, responsive to a second mode of operation.