US 12,436,766 B2
Sharing branch predictor resource for instruction cache and trace cache predictions
Muawya M. Al-Otoom, Lake Oswego, OR (US); Niket K. Choudhary, Santa Clara, CA (US); and Pruthivi Vuyyuru, Santa Clara, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jul. 14, 2023, as Appl. No. 18/352,351.
Prior Publication US 2025/0021337 A1, Jan. 16, 2025
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3804 (2013.01) [G06F 9/3808 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
processor circuitry configured to execute instructions, including control transfer instructions (CTIs);
fetch circuitry configured to fetch a group of multiple instructions for the processor circuitry in a given clock cycle;
trace cache circuitry configured to identify and store instruction traces that include multiple predicted-taken control transfer instructions;
prediction circuitry that includes:
table circuitry configured to store multiple prediction tables, including:
a base table; and
multiple levels of tagged geometric length (TAGE) tables;
CTI predictor lane circuitry configured to access the prediction tables to predict directions of multiple control transfer instructions in a given fetch group; and
trace predictor lane circuitry configured to access the prediction tables to predict a direction of a final control transfer instruction in a trace cached by the trace cache circuitry, including to use a dedicated prediction field in one or more entries of the base table and share the TAGE tables with the CTI predictor lane circuitry.