US 12,436,765 B2
Data processing apparatus, chip, and data processing method
Fei Luo, Beijing (CN); and Weiwei Wang, Beijing (CN)
Assigned to Stream Computing, Inc., Beijing (CN)
Filed by Stream Computing Inc., Beijing (CN)
Filed on Oct. 25, 2022, as Appl. No. 18/049,483.
Application 18/049,483 is a continuation of application No. PCT/CN2021/086850, filed on Apr. 13, 2021.
Prior Publication US 2023/0069032 A1, Mar. 2, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 15/80 (2006.01)
CPC G06F 9/30181 (2013.01) [G06F 9/3877 (2013.01); G06F 9/3885 (2013.01); G06F 15/8007 (2013.01); G06F 15/8046 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A data processing apparatus, comprising:
a plurality of processing cores having a preset execution sequence, the plurality of processing cores including a head processing core and at least one other processing core; and
a synchronization generator, configured to generate a synchronization signal after receiving a synchronization request signal sent by each of the plurality of processing cores, and send the synchronization signal to each of the processing cores;
wherein in a cycle of a current synchronization signal:
the head processing core is configured to send an instruction according to the synchronization signal, and receive and execute a program obtained according to the instruction; and
each of the at least one other processing cores is configured to receive and execute a program sent by a respective previous processing core in the preset execution sequence, wherein the program sent by the respective previous processing core has been executed by the respective previous processing core in a cycle of a previous synchronization signal.