US 12,436,761 B2
Instruction applicable to radix-3 butterfly computation
Saurabh Lahoti, Westford, MA (US); Marc Hoffman, Mansfield, MA (US); Srijesh Sudarsanan, Boston, MA (US); and Hongfeng Dong, Acton, MA (US)
Assigned to Qualcomm Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/448,828.
Prior Publication US 2023/0102798 A1, Mar. 30, 2023
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/3001 (2013.01) [G06F 9/30036 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A device comprising:
a memory configured to store instructions including a first radix-2 butterfly instruction, a particular instruction, and a second radix-2 butterfly instruction; and
a processor coupled to the memory and configured to receive and execute the first radix-2 butterfly instruction, the particular instruction, and the second radix-2 butterfly instruction during a radix-3 butterfly computation of a discrete Fourier transform operation or an inverse discrete Fourier transform operation, wherein the processor is configured to execute the particular instruction to:
in a first phase of execution of the particular instruction:
generate, at an arithmetic unit of the processor, first output data corresponding to a sum of first input data obtained from a first input vector register indicated by one or more parameters of the particular instruction and second input data obtained from a second input vector register indicated by the one or more parameters of the particular instruction, the second input data comprising a first output generated during execution of the first radix-2 butterfly instruction; and
perform, at divide circuitry of the processor that is coupled to the arithmetic unit, a divide operation on the second input data; and
in a second phase of execution of the particular instruction:
generate, at the arithmetic unit, second output data corresponding to a difference of the first input data and a result of the divide operation.