US 12,436,740 B2
High throughput linear feedback shift register
Ankur Bal, Greater Noida (IN); Abhishek Kishore Kaul, Himachal Pradesh (IN); and Jeet Narayan Tiwari, Greater Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Aug. 4, 2021, as Appl. No. 17/393,492.
Claims priority of provisional application 63/072,376, filed on Aug. 31, 2020.
Prior Publication US 2022/0066498 A1, Mar. 3, 2022
Int. Cl. G06F 7/58 (2006.01)
CPC G06F 7/584 (2013.01) 23 Claims
OG exemplary drawing
 
1. An N-bit linear feedback shift register (LFSR), comprising:
a number P of parallel chains of flip flops each having an output;
a counter circuit clocked by a first clock and configured to output N different output words, with a different one of the N different output words being produced at each pulse of the first clock, and configured to reset once each of the N different output words has been output;
a multiplexer having a singular output, and having inputs coupled to the outputs of the P parallel chains of flip flops, having a selection input coupled to the counter circuit to receive the N different output words from the counter circuit, and configured to pass a different input to the singular output dependent upon which of the N different output words is received from the counter circuit; and
a flip flop having an input coupled to the singular output of the multiplexer and being clocked by the first clock such that the flip flop passes a current state of its input to its output upon each pulse of the first clock;
wherein each parallel chain of flip flops comprises:
a chain of flip flops clocked by a second clock, the second clock being equal to the first clock divided by P, each flip flop of that chain except a last flip flop of that chain having an index calculated as x+yP, where x represents which of the P parallel chains of flip flops that the chain of flip flops belongs to, and where y represents a position within the chain of flip flops occupied by that flip flop, wherein the last flip flop of that chain has an index calculated as x+yP where y is equal to a smallest integer greater than or equal to (N−1−x)/P; and
a combinational logic circuit for that parallel chain of flips receiving, as input, output from those flip flops of the chain of flip flops for that parallel chain of flip flops having an index equal to an exponent of a primitive polynomial of order N−1, wherein the combinational logic circuit for that parallel chain of flip flops provides its output as input to a first of the chain of flip flops for that parallel chain of flip flops.