US 12,436,739 B1
Non-linear polar material based low power multiplier with transmission-gate based reset mechanism
Amrita Mathuriya, Portland, OR (US); Rafael Rios, Austin, TX (US); Ikenna Odinaka, Durham, NC (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Oct. 1, 2021, as Appl. No. 17/449,748.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 7/501 (2006.01); H03K 19/20 (2006.01); H03K 19/23 (2006.01)
CPC G06F 7/501 (2013.01) [H03K 19/20 (2013.01); H03K 19/23 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a 1-bit full adder comprising a majority gate or a minority gate, wherein the 1-bit full adder comprises non-linear polar material; and
a reset mechanism to reset nodes coupled to the non-linear polar material during a reset phase separate from an evaluation phase,
wherein the reset mechanism includes:
a first transmission gate at an output of an AND gate coupled to the 1-bit full adder;
a second transmission gate at an output of a 3-input majority gate of the 1-bit full adder; and
a third transmission gate at an output of a 5-input majority gate of the 1-bit full adder.