US 12,436,716 B2
Method and system for performing read and write operations in cells of a NAND memory
Anantha Sharma, Bengaluru (IN); Pandi Kanniah, Bengaluru (IN); Sharath Kumar Kodase, Bengaluru (IN); Suman Prakash Balakrishnan, Bengaluru (IN); and Sandeep Kumar Ananthapalli, Bengaluru (IN)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 10, 2023, as Appl. No. 18/349,356.
Claims priority of application No. 202341033728 (IN), filed on May 12, 2023.
Prior Publication US 2024/0377987 A1, Nov. 14, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for writing data into cells of a NOT-AND (NAND) memory, the NAND memory including a plurality of non-volatile memory cells and one or more volatile NAND latches configured to temporarily store data before writing the data to the plurality of non-volatile memory cells, the method comprising:
receiving, by a memory controller of the NAND memory, a write request from a host controller to write data present in a set of support cell blocks of the NAND memory into a ‘n’-level cell block of the NAND memory, wherein the write request comprises information on mapping from each page of the set of support cell blocks to a corresponding page in the ‘n’-level cell block;
updating, by the memory controller, a Logical to Physical (L2P) table based on the mapping between the set of support cell blocks and the ‘n’-level cell block; and
performing, by the memory controller, a copyback operation on the set of support cell blocks for writing the data to the ‘n’-level cell block based on the L2P table using the one or more volatile NAND latches as hardware accelerators configured to perform the copyback operation as an internal copyback operation without the host controller tracking intermediate single-level cell (SLC) locations in the L2P table.