US 12,436,713 B2
Memory system using host memory buffer and operation method thereof
Bumhee Lee, Suwon-si (KR); Wooram Kim, Suwon-si (KR); Hyunseok Kim, Suwon-si (KR); Kihyun Park, Suwon-si (KR); Sooyun Lee, Suwon-si (KR); Hyeongyu Cho, Suwon-si (KR); and Shin-Ho Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 13, 2024, as Appl. No. 18/662,090.
Application 18/662,090 is a continuation of application No. 17/979,554, filed on Nov. 2, 2022, granted, now 12,014,080.
Claims priority of application No. 10-2021-0154276 (KR), filed on Nov. 10, 2021; and application No. 10-2022-0055613 (KR), filed on May 4, 2022.
Prior Publication US 2024/0295988 A1, Sep. 5, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 1/3203 (2019.01); G06F 12/02 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 1/3203 (2013.01); G06F 3/0604 (2013.01); G06F 3/0622 (2013.01); G06F 3/0679 (2013.01); G06F 12/0223 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An operation method of a storage device which shares a portion of a host memory of a host as a host memory buffer, the method comprising:
receiving a command to enable the host memory buffer;
receiving information about a response speed of the host memory buffer; and
operating the host memory buffer based on the response speed of the host memory buffer,
wherein the information about the response speed of the host memory buffer comprising a first response speed level, among a plurality of response speed levels, and
wherein the operating the host memory buffer based on the response speed of the host memory buffer comprises controlling the host memory buffer to operate in a first mode, among a plurality of modes, based on the first response speed level.