US 12,436,711 B2
Providing fine grain access to package memory
Abhishek Anil Sharma, Portland, OR (US); Wilfred Gomes, Portland, OR (US); Rajabali Koduri, Saratoga, CA (US); and Pushkar Ranade, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 30, 2022, as Appl. No. 17/708,398.
Prior Publication US 2023/0315334 A1, Oct. 5, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 12/1027 (2016.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 12/1027 (2013.01); G06F 2212/68 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first die having a plurality of cores, each of the plurality of cores comprising:
a scheduler to schedule tasks for execution on an execution circuit;
the execution circuit to execute the tasks;
and a local memory interface circuit to access a local portion of a dynamic random access memory (DRAM);
a second die comprising the DRAM, the DRAM comprising a plurality of local portions, wherein at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by a stacking of the first die and the second die; wherein each of the plurality of cores further comprises an interface circuit to couple the core to a first nearest neighbor core and a second nearest neighbor core, wherein the interface circuit is to store a first processed data in the corresponding local portion of the DRAM, and to send the first processed data to the local memory portion of the first nearest neighbor core, wherein the first nearest neighbor core is to further process the first processed data.