US 12,436,710 B2
Techniques for sequential access operations
Giuseppe Cariello, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 14, 2024, as Appl. No. 18/663,980.
Application 18/663,980 is a continuation of application No. 17/663,797, filed on May 17, 2022, granted, now 12,014,073.
Prior Publication US 2024/0385771 A1, Nov. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
non-volatile memory; and
processing circuitry coupled with the non-volatile memory, wherein the processing circuitry is configured to cause the memory system to:
receive, at the memory system, a first plurality of write commands associated with first data;
store, in the non-volatile memory based at least in part on receiving the first plurality of write commands, an indication of a starting logical address associated with the first data;
store, in the non-volatile memory based at least in part on determining that the first plurality of write commands are associated with a sequential write mode, an indication of the sequential write mode;
detect a condition to store an indication of a second logical address associated with the first data in the non-volatile memory; and
suppress storing the indication of the second logical address in the non-volatile memory based at least in part on the indication of the sequential write mode.