US 12,436,705 B2
Dynamically scalable and partitioned copy engine
Nilay Mistry, Bangalore (IN); David Puffer, Tempe, AZ (US); Prasoonkumar Surti, Folsom, CA (US); and Hema Chand Nalluri, Bangalore (IN)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,914.
Prior Publication US 2022/0413704 A1, Dec. 29, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 9/38 (2018.01); G06F 13/40 (2006.01)
CPC G06F 3/065 (2013.01) [G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0673 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 9/38885 (2023.08); G06F 13/4027 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, by a copy engine hardware circuitry of a graphics processor, configuration information for a graphics processor, the configuration information comprising a number of partitions of the processor and a size of each of the partitions;
configuring a number of copy front-ends of the copy engine hardware circuitry based on the number of partitions, wherein each partition is assigned a copy front-end;
configuring a number of copy back-ends of the copy engine hardware circuitry based on the size of each of the partitions, wherein each copy front-end is assigned one or more of the copy back-ends, and wherein each of the copy front-ends and the one or more of the copy back-ends hardware circuitry that is assigned to the single each of the copy front-ends is to form a copy engine building block of the copy engine hardware circuitry;
configuring sub-networks of a connectivity matrix, wherein each set of copy front-end and corresponding one or more copy back-ends is communicably coupled via one of the sub-networks; and
responsive to one of the partitions being reconfigured, resetting the copy engine building block corresponding to the one of the partitions being reconfigured to an unassigned state by resetting the copy front-end hardware circuitry associated with the one of the partitions and draining to an idle state the subset of copy back-end hardware circuitry corresponding to the copy front-end hardware circuitry being reset.