US 12,436,699 B2
Integrated circuit data stream processing using paged buffering
Kunihiko Ietomi, Kanagawa (JP); Nikolay Nez, Tokyo (JP); Oleg Khavin, Tokyo (JP); and Sakyasingha Dasgupta, Tokyo (JP)
Assigned to EDGECORTIX INC., Tokyo (JP)
Filed by EDGECORTIX INC., Tokyo (JP)
Filed on Feb. 28, 2024, as Appl. No. 18/589,430.
Claims priority of provisional application 63/502,417, filed on May 16, 2023.
Prior Publication US 2024/0385761 A1, Nov. 21, 2024
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
17. A method comprising:
performing operations, by a processor of an integrated circuit in response to determining that a local read counter of the integrated circuit includes a value indicating at least one accessible block of data is stored in an upstream memory of the integrated circuit and a local write counter of the integrated circuit includes a value indicating at least one downstream page of a downstream memory of the integrated circuit is available for recording, the operations including:
adjusting the local read counter to indicate a page release,
adjusting the local write counter to indicate a page occupy,
reading a first block of data recorded to the upstream memory,
processing the first block of data to produce a second block of data, and
recording the second block of data to a downstream memory of the integrated circuit.