US 12,436,694 B2
Configurable memory die capacitance
Jingwei Cheng, Shanghai (CN); and Cheng Zhang, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 13, 2024, as Appl. No. 18/604,203.
Application 18/604,203 is a continuation of application No. 16/976,286, granted, now 11,947,813, previously published as PCT/CN2019/103342, filed on Aug. 29, 2019.
Prior Publication US 2024/0295975 A1, Sep. 5, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01)
CPC G06F 3/0629 (2013.01) [G06F 3/0679 (2013.01); G06F 13/1668 (2013.01); G11C 7/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a conductive path;
a plurality of memory dies each comprising:
a respective input/output (I/O) pad coupled with the conductive path of the memory device; and
a respective capacitive component coupled with the respective I/O pad and having an adjustable capacitance; and
circuitry coupled with the plurality of memory dies and configured to cause the memory device to:
receive first configuration information associated with a first adjustable capacitance of a first respective capacitive component of the respective capacitive components of the plurality of memory dies;
configure the first adjustable capacitance of the first respective capacitive component based at least in part on receiving the first configuration information;
receive second configuration information associated with a second adjustable capacitance of a second respective capacitive component of the respective capacitive components of the plurality of memory dies; and
configure the second adjustable capacitance of the second respective capacitive component based at least in part on receiving the second configuration information.