US 12,436,692 B2
Peak power management data burst communication
Hojung Yun, San Jose, CA (US); Liang Yu, Boise, ID (US); and Jonathan S. Parry, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 16, 2023, as Appl. No. 18/234,522.
Claims priority of provisional application 63/399,257, filed on Aug. 19, 2022.
Prior Publication US 2024/0061593 A1, Feb. 22, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory dies, each memory die of the plurality of memory dies comprising;
a memory array; and
control logic, operatively coupled with the memory array, to perform operations for implementing peak power management (PPM) data burst communication, the operations comprising:
monitoring a data burst with respect to the memory array;
detecting a current reservation trigger associated with the data burst;
in response detecting the current reservation trigger, reserving an initial amount of current reflecting a maximum current consumption value associated with a maximum data transfer speed of the data burst;
detecting a plurality of input/output cycles of the data burst following a preamble period of the data burst; and
in response to detecting the plurality of input/output cycles, reserving, based on an analysis of the plurality of input/output cycles, a subsequent amount of current reflecting an actual current consumption value associated with an actual data transfer speed of the data burst.