US 12,436,686 B2
Enhanced bit error rate estimation scan process
Yichen Wang, Shanghai (CN); Ming Wang, Shanghai (CN); Anubhav Khandelwal, San Jose, CA (US); and Liang Li, Shanghai (CN)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Dec. 20, 2023, as Appl. No. 18/390,296.
Prior Publication US 2025/0208764 A1, Jun. 26, 2025
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory block including an array of memory cells that are arranged in a plurality of word lines an in a plurality of NAND strings, the plurality of NAND strings being divided into a plurality of string groups; and
control circuitry configured to:
in a first string group of the plurality of string groups, perform a broad voltage level range bit error rate estimation scan to identify an approximate optimal read reference voltage for the first string group;
in the first string group, perform a narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage, to determine an optimal read reference voltage for the first string group; and
in a second string group of the plurality of string groups, without performing the broad voltage level range bit error rate estimate scan, perform the narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage for the first string group, to determine an optimal read reference voltage for the second string group,
wherein the broad voltage level range bit error rate estimation scan includes scanning a broader range of voltage levels than the narrow voltage level range bit error rate estimation scan.