US 12,436,685 B2
Memory device for performing program operation according to incremental step pulse programming method, storage device including the same, and operating method of the memory device
Hyung Jin Choi, Icheon-si (KR); Gwi Han Ko, Icheon-si (KR); Chan Hui Jeong, Icheon-si (KR); and Se Chun Park, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 4, 2023, as Appl. No. 18/312,459.
Claims priority of application No. 10-2022-0162904 (KR), filed on Nov. 29, 2022.
Prior Publication US 2024/0176503 A1, May 30, 2024
Int. Cl. G11C 16/04 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0659 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory cells;
a peripheral circuit configured to perform a plurality of program loops each including a program voltage apply operation of applying a program voltage to selected memory cells, among the plurality of memory cells, and a verify operation of verifying a program state of the selected memory cells; and
a control logic configured to control the peripheral circuit to apply program voltages increasing in a step-wise manner by a first step voltage in program loops in a first state, among the plurality of program loops, and increasing in a step-wise manner by a second step voltage in program loops in a second state that occur after the program loops in the first state,
wherein the second step voltage is lower than the first step voltage, and
wherein the first state and the second state of the program loops are determined based on when a verify operation on a program state having a highest threshold voltage is performed.