US 12,436,595 B2
Distributed thermal management architecture
Louis Louie, San Diego, CA (US); Ronald Alton, Oceanside, CA (US); Sumarlin William, San Diego, CA (US); and Vinayak Nana Mehetre, Bangalore (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 21, 2023, as Appl. No. 18/452,880.
Prior Publication US 2025/0068227 A1, Feb. 27, 2025
Int. Cl. G06F 1/32 (2019.01); G06F 1/20 (2006.01); G06F 1/3206 (2019.01); G06F 1/3287 (2019.01)
CPC G06F 1/3287 (2013.01) [G06F 1/206 (2013.01); G06F 1/3206 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for implementing thermal management, the apparatus comprising:
a serial databus;
a central processing unit (CPU) coupled to the serial databus;
a graphics processing unit (GPU) coupled to the serial databus;
a neural signal processor (NSP) coupled to the serial databus;
an always on subsystem (AOSS) coupled to the serial databus; wherein the serial databus, the CPU, the GPU, the NSP and the AOSS are implemented on a system on a chip (SOC);
wherein the CPU comprises a first plurality of thermal sensors and a first plurality of controllers, and each of the first plurality of thermal sensors is coupled to each of the first plurality of controllers;
wherein the GPU comprises a second plurality of thermal sensors and a second plurality of controllers, and each of the second plurality of thermal sensors is coupled to each of the second plurality of controllers;
wherein the NSP comprises a third plurality of thermal sensors and a third plurality of controllers, and each of the third plurality of thermal sensors is coupled to each of the third plurality of controllers; and
wherein the AOSS comprises a fourth plurality of thermal sensors and a fourth plurality of controllers, and each of the fourth plurality of thermal sensors is coupled to each of the fourth plurality of controllers.