US 12,436,592 B2
Low power low frequency counter for software use
Subrata Roy, Austin, TX (US)
Assigned to Silicon Laboratories Inc., Austin, TX (US)
Filed by Silicon Laboratories Inc., Austin, TX (US)
Filed on May 22, 2023, as Appl. No. 18/321,058.
Prior Publication US 2024/0393857 A1, Nov. 28, 2024
Int. Cl. G06F 1/324 (2019.01); G06F 1/04 (2006.01); G06F 1/06 (2006.01); G06F 1/08 (2006.01); G06F 1/14 (2006.01); G06F 1/3203 (2019.01); G06F 1/3237 (2019.01); G06F 1/3287 (2019.01)
CPC G06F 1/324 (2013.01) [G06F 1/08 (2013.01); G06F 1/14 (2013.01); G06F 1/04 (2013.01); G06F 1/06 (2013.01); G06F 1/3203 (2013.01); G06F 1/3237 (2013.01); G06F 1/3287 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for operating an integrated circuit device having a low power mode of operation and an active mode of operation, the method comprising:
updating a low frequency count value in the active mode and maintaining the low frequency count value at a fixed value in the low power mode,
wherein in the active mode, the low frequency count value is updated at a rate equal to a first frequency, and
wherein updating the low frequency count value comprises:
updating a fractional count in response to a first clock signal;
updating an integral count in response to a second clock signal;
generating the second clock signal based on the fractional count and the first clock signal; and
adjusting the low frequency count value in response to exiting the low power mode and based on a difference between a current value of a real time clock counter and a prior value of the real time clock counter stored upon entry into the low power mode,
wherein the second clock signal causes the integral count to update at an average rate equal to the first frequency, and
wherein the first clock signal has a second frequency, the first frequency being lower than the second frequency.