US 12,436,590 B2
Time synchronization of collecting and reporting power events between hierarchical power throttling circuits in a hierarchical power management system
Vinod Chamarty, Campbell, CA (US); Sagar Koorapati, Austin, TX (US); Sreeram Jayadev, Austin, TX (US); and Alon Naveh, Corte Madera, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jun. 22, 2023, as Appl. No. 18/339,430.
Prior Publication US 2024/0427392 A1, Dec. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/3206 (2019.01); G06F 1/26 (2006.01); G06F 1/3234 (2019.01)
CPC G06F 1/3206 (2013.01) [G06F 1/26 (2013.01); G06F 1/3243 (2013.01)] 39 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) chip comprising:
a plurality of processing devices each coupled to at least one power rail; and
a master clock circuit configured to generate a master clock signal comprising a plurality of first pulses of a first frequency;
a hierarchical power management system, comprising:
a plurality of local area management (LAM) circuits, comprising:
a local clock circuit configured to generate a local clock signal defining a plurality of local time windows each comprising a defined number of local pulses of the local clock signal;
the plurality of LAM circuits each configured to:
for each local time window of the plurality of local time windows:
synchronize an initial local pulse of the local time window based on the master clock signal;
sample processing activity of at least one processing device of a subset of the plurality of processing devices within the local time window comprising the defined number of local pulses of the local clock signal to generate a plurality of activity samples;
determine a current flow rate of the at least one processing device within the local time window based on the plurality of activity samples;
estimate power consumption of the at least one processing device based on the plurality of activity samples within the local time window; and
generate an activity power event based on the estimated power consumption of the at least one processing device for the local time window; and
a power estimation and limiting (PEL) circuit comprising:
a second clock circuit configured to generate a second clock signal defining a plurality of second time windows each comprising a defined number of second pulses of the second clock signal;
the PEL circuit configured to:
for each second time window of the plurality of second time windows:
synchronize an initial second pulse in the second time window based on the master clock signal;
receive the plurality of activity power events generated by the plurality of LAM circuits within the second time window; and
generate a power limiting management response to cause power consumption to be throttled in the IC chip based on the received plurality of activity power events for the second time window.