| CPC G06F 1/185 (2013.01) [G06F 9/5016 (2013.01); G06F 13/4022 (2013.01); G06F 13/409 (2013.01)] | 19 Claims |
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1. A memory system, comprising:
a first motherboard, and a processor and a high-speed interconnection channel interface that are integrated on the first motherboard;
a first adapter board, and a high-speed interconnection channel interface, a chip and a memory module that are integrated on the first adapter board; and
at least one connecting cable;
wherein the at least one connecting cable is used to establish a physical link between the high-speed interconnection channel interface of the first motherboard and the high-speed interconnection channel interface of the first adapter board, to establish a communication connection between the first motherboard and the first adapter board; wherein a connection between the high-speed interconnection channel interface of the first motherboard and the high-speed interconnection channel interface of the first adapter board is used to transmit a high-speed channel interconnection signal;
the at least one connecting cable is further used to convert the high-speed channel interconnection signal into a processor internal dedicated bus signal transmitted by a physical link based on a peripheral component interconnect express; and
the chip of the first adapter board is used to acquire the converted processor internal dedicated bus signal, and convert the processor internal dedicated bus signal into a double data rate memory signal, to enable a memory resource of the memory module of the first adapter board to be accessed and used by the processor of the first motherboard, to achieve memory pooling;
the memory system further comprises:
a second motherboard, and a processor and a high-speed interconnection channel interface that are integrated on the second motherboard;
wherein the at least one connecting cable is further used to establish a physical link between the high-speed interconnection channel interface of the first motherboard and the high-speed interconnection channel interface of the second motherboard, to establish a communication connection between the first motherboard and the second motherboard;
the memory system further comprises a second adapter board with a same structure as the first adapter board; the second adapter board is used to be connected to the second motherboard;
wherein a memory resource adjustment apparatus in the memory system is configured to determine current load information of the memory system, and determine a target memory resource that needs to be provided according to the current load information; and
based on the target memory resource, determine whether to control the first motherboard and the first adapter board to connect, and/or, determine whether to control the second motherboard and the second adapter board to connect, and/or, determine a quantity of first adapter boards connected to the first motherboard, and/or, determine a quantity of second adapter boards connected to the second motherboard;
wherein the at least one connecting cable comprises a first connecting cable and a second connecting cable, and the memory system further comprises:
the first connecting cable, used to transmit data between the processor of the first motherboard and the processor of the second motherboard; and
the second connecting cable, used to transmit a logic control signal between the first motherboard and the second motherboard.
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