US 12,436,558 B2
Hybrid clocking scheme for SERDES physical layer circuits
Nitz Saputra, San Diego, CA (US); and Sameer Wadhwa, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Nov. 15, 2023, as Appl. No. 18/509,643.
Prior Publication US 2025/0155917 A1, May 15, 2025
Int. Cl. G06F 1/08 (2006.01)
CPC G06F 1/08 (2013.01) 9 Claims
OG exemplary drawing
 
1. A clock generation circuit, comprising:
a first inverter coupled to an input clock signal and comprising driver slices, each driver slice in the first inverter comprising:
a first pair of transistors that have gates that are coupled to the input clock signal;
a second pair of transistors that includes a first transistor that has a source coupled to a higher voltage rail of a power supply and a drain coupled to a source of a first transistor in the first pair of transistors, and a second transistor that has a source coupled to a lower voltage rail of the power supply and a drain coupled to a source of a second transistor in the first pair of transistors, wherein the second pair of transistors is turned on when a first differential enable signal is in a first signaling state and turned off when the first differential enable signal is in a second signaling state; and
a first tuning resistor coupled to the drains of the first pair of transistors and further coupled to an output of the first inverter;
a first tunable capacitor coupled to the output of the first inverter; and
a second inverter that has an input coupled to the output of the first inverter and that outputs a quadrature version of the input clock signal, wherein the second inverter comprises
a third pair of transistors that have gates that are coupled to the output of the first inverter;
a fourth pair of transistors that includes a first transistor that has a source coupled to the higher voltage rail of the power supply and a drain coupled to a source of a first transistor in the third pair of transistors, and a second transistor that has a source coupled to the lower voltage rail of the power supply and a drain coupled to a source of a second transistor in the third pair of transistors, wherein the fourth pair of transistors is turned on when a second differential enable signal is in the first signaling state and turned off when the second differential enable signal is in the second signaling state;
a second tuning resistor coupled to the drains of the third pair of transistors and to an output of the second inverter; and
a second tunable capacitor coupled to the output of the second inverter.