US 12,436,556 B2
Communication protocol for die to die interface
Joachim Josef Maria Kruecken, Munich (DE); and Andreas Laudenbach, Haag (DE)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Sep. 15, 2023, as Appl. No. 18/468,263.
Prior Publication US 2025/0093899 A1, Mar. 20, 2025
Int. Cl. G05F 3/08 (2006.01); H03K 3/037 (2006.01); H03K 5/24 (2006.01)
CPC G05F 3/08 (2013.01) [H03K 3/037 (2013.01); H03K 5/24 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a receiver circuit configured to receive an input voltage waveform from a single wire and configured to generate an output bit stream corresponding to the input voltage waveform, the receiver comprising:
a voltage level determination circuit configured to indicate whether a voltage level of the input voltage waveform has one of a high level that is higher than a high voltage threshold, a low level that is lower than a low voltage threshold, or a mid level that is between the high and low voltage levels, wherein the high voltage threshold is greater than the low voltage threshold; and
a bit value generator configured to provide a next bit value of the output bit stream as a first value when the voltage level is the high level, as a second value when the voltage level is the low level, and as a same value as an immediately previous bit value of the output bit stream when the voltage level is the mid level, wherein the first value and the second value correspond to opposite logic states.