US 12,436,504 B2
Using time-to-digital converters to delay signals with high accuracy and large range
Krishnan Balakrishnan, Austin, TX (US); and James David Barnette, Austin, TX (US)
Assigned to Skyworks Solutions, Inc., Irvine, CA (US)
Filed by Skyworks Solutions, Inc., Irvine, CA (US)
Filed on May 24, 2024, as Appl. No. 18/673,897.
Application 18/673,897 is a continuation of application No. 17/990,147, filed on Nov. 18, 2022, granted, now 12,019,406.
Application 17/990,147 is a continuation of application No. 16/428,288, filed on May 31, 2019, granted, now 11,526,135, issued on Dec. 13, 2022.
Prior Publication US 2025/0021055 A1, Jan. 16, 2025
This patent is subject to a terminal disclaimer.
Int. Cl. G04F 10/00 (2006.01); G06F 1/08 (2006.01); H03K 5/00 (2006.01); H03L 7/081 (2006.01); H03L 7/093 (2006.01)
CPC G04F 10/005 (2013.01) [G06F 1/08 (2013.01); H03K 5/00 (2013.01); H03L 7/0814 (2013.01); H03K 2005/00058 (2013.01); H03L 7/093 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of operating a phase-locked loop comprising:
with a first time-to-digital converter, converting first edges of a first clock signal to first digital values using output values of a counter circuit;
with a second time-to-digital converter, converting second edges of a second clock signal to second digital values using output values of the counter circuit;
with a third time-to-digital converter, converting third edges of a third clock signal to third digital values using output values of the counter circuit;
storing the first digital values and the second digital values in first and second queues within at least one memory;
outputting each respective value of the first digital values and the second digital values from the memory after a first period of delay elapses following storing the respective value in the memory; and
sequentially receiving and processing the first digital values and the second digital values output from the memory using a phase and frequency detector of the phase-locked loop.