US 12,436,467 B2
Simulating die rotation to minimize area overhead of reticle stitching for stacked dies
Scott Siers, Elk Grove, CA (US); Satish Damaraju, El Dorado Hills, CA (US); and Christopher Pelto, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/561,524.
Prior Publication US 2023/0205094 A1, Jun. 29, 2023
Int. Cl. H01L 23/48 (2006.01); G03F 7/00 (2006.01); H01L 23/498 (2006.01)
CPC G03F 7/70475 (2013.01) [H01L 23/481 (2013.01); H01L 23/49816 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a monolithic base die comprising a first region and a second region, the first and second regions comprising shared patterns for a device layer and a plurality of first metallization layers of the first and second regions;
a plurality of first through vias in a first portion of the first region and a plurality of second through vias in a second portion of the second region, the first and second through vias extending vertically across the device layer and the first metallization layers, and the first and second portions having a same relative location within the first and second regions, respectively; and
one or more second metallization layers over the first through vias and one or more third metallization layers over the second through vias, the second metallization layers coupled to a first subset of the first through vias and the third metallization layers coupled to a second subset of the second through vias.