US 12,436,337 B2
Low loss optical interposer
Gabriel Joel Mendoza, Mountain View, CA (US); Khanh Tran, Milpitas, CA (US); Wenguang Li, Milpitas, CA (US); Vimal Kamineni, Fremont, CA (US); and Mark Thompson, Chester (GB)
Assigned to PsiQuantum, Corp., Palo Alto, CA (US)
Appl. No. 19/112,878
Filed by PsiQuantum, Corp., Palo Alto, CA (US)
PCT Filed Sep. 19, 2024, PCT No. PCT/US2024/047487
§ 371(c)(1), (2) Date Mar. 18, 2025,
PCT Pub. No. WO2025/064676, PCT Pub. Date Mar. 27, 2025.
Claims priority of provisional application 63/540,024, filed on Sep. 22, 2023.
Prior Publication US 2025/0258339 A1, Aug. 14, 2025
Int. Cl. G02B 6/132 (2006.01); H10F 71/00 (2025.01)
CPC G02B 6/132 (2013.01) [H10F 71/136 (2025.01); H10F 71/139 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a first oxide layer on a photonic integrated circuit (PIC) wafer, the PIC wafer comprising a substrate layer and a PIC waveguide layer, the PIC waveguide layer comprising a plurality of PIC waveguides, the first oxide layer being deposited on the PIC waveguide layer;
planarizing the first oxide layer;
bonding a carrier wafer to the PIC wafer to form a bonded wafer, the carrier wafer comprising a support layer;
removing the substrate layer from the bonded wafer;
singulating the bonded wafer to form a plurality of carrier PIC chips;
positioning the PIC carrier chip on an interposer wafer, the interposer wafer comprising an interposer substrate layer and an interposer waveguide layer on the interposer substrate layer, the interposer waveguide layer comprising a plurality of interposer waveguides;
bonding the PIC carrier chip to the interposer wafer to form a PIC chip interposer structure;
removing the support layer from the PIC chip interposer structure, wherein the removing of the support layer exposes an oxide layer; and
planarizing the oxide layer, wherein the oxide layer is planarized using chemical mechanical polishing.