US 12,436,192 B2
Semiconductor integrated circuit and test method for semiconductor integrated circuit
Tomoyuki Maekawa, Fujisawa Kanagawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Kawasaki (JP); and Toshiba Electronic Devices & Storage Corporation, Kawasaki (JP)
Filed by Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed on Sep. 8, 2023, as Appl. No. 18/244,162.
Claims priority of application No. 2023-049571 (JP), filed on Mar. 27, 2023.
Prior Publication US 2024/0329132 A1, Oct. 3, 2024
Int. Cl. G01R 31/317 (2006.01); G01R 31/3185 (2006.01)
CPC G01R 31/318552 (2013.01) [G01R 31/31727 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit comprising:
a core circuit including a first scan layer and a second scan layer, the first scan layer including a first scan chain circuit and a first combinational circuit, the second scan layer including a second scan chain circuit and a second combinational circuit; and
a test control circuit that controls a scan test on the first and second scan layers;
wherein
the test control circuit
supplies a first piece of test data and a first shift clock to the first scan layer and then sets the first scan layer to a waiting state,
supplies a second piece of test data and a second shift clock to the second scan layer during a period in which the first scan layer is in the waiting state,
sets the second scan layer to a waiting state after supplying the second piece of test data and the second shift clock to the second scan layer, and
supplies a first launch clock and a first capture clock to the first scan layer after setting the second scan layer to the waiting state.