US 12,436,186 B2
Self-reset testing systems and methods
Camilo Montenegro, San Jose, CA (US); Mei-Mei Su, San Jose, CA (US); and Linden Hsu, San Jose, CA (US)
Assigned to ADVANTEST CORPORATION, Tokyo (JP)
Filed by ADVANTEST CORPORATION, Tokyo (JP)
Filed on Mar. 31, 2023, as Appl. No. 18/129,490.
Claims priority of provisional application 63/439,430, filed on Jan. 17, 2023.
Claims priority of provisional application 63/434,024, filed on Dec. 20, 2022.
Prior Publication US 2024/0201251 A1, Jun. 20, 2024
Int. Cl. G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/319 (2006.01)
CPC G01R 31/2889 (2013.01) [G01R 31/31727 (2013.01); G01R 31/31907 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the test board includes an FPGA; and
a tester configured to direct testing of the plurality of DUTs, wherein a host in the tester is communicatively coupled to the FPGA, wherein the test board includes logic to internally generate a simulated reset stable indication for the FPGA, and wherein the simulated reset stable indication is an indication that an externally supplied resource is stable.