US 12,108,691 B2
Manufacturing method of memory device
Chich-Neng Chang, Pingtung County (TW); Da-Jun Lin, Kaohsiung (TW); Shih-Wei Su, Tainan (TW); Fu-Yu Tsai, Tainan (TW); and Bin-Siang Tsai, Changhua County (TW)
Assigned to United Microelectronics Corp., Hsinchu (TW)
Filed by United Microelectronics Corp., Hsinchu (TW)
Filed on May 26, 2023, as Appl. No. 18/324,173.
Application 18/324,173 is a division of application No. 17/140,981, filed on Jan. 4, 2021, granted, now 11,707,003.
Claims priority of application No. 202011388129.6 (CN), filed on Dec. 1, 2020.
Prior Publication US 2023/0301210 A1, Sep. 21, 2023
Int. Cl. H10N 70/20 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/24 (2023.02) [H10B 63/30 (2023.02); H10N 70/063 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A manufacturing method of a memory device, the manufacturing method comprising:
sequentially forming a bottom electrode layer, a resistance variable material layer, a top electrode layer and a hard mask layer on a device substrate, wherein the bottom electrode layer is formed with a tensile stress, and the top electrode layer is formed with a compressive stress;
patterning the hard mask layer, to form a hard mask;
removing portions of the top electrode layer, the resistance variable material layer and the bottom electrode layer by using the hard mask as a shadow mask, to form a top electrode, a resistance variable layer and a bottom electrode, respectively;
removing the hard mask.